教師資料查詢 | 類別: 專書單篇 | 教師: 李世安SHIH-AN, LI (瀏覽個人網頁)

標題:Hardware accelerator design for image processing
學年101
學期1
出版(發表)日期2012/08/01
作品名稱Hardware accelerator design for image processing
作品名稱(其他語言)
著者Li, Shih-An; Wong, Ching-Chang; Yang, Ching-Yang; Chen, Li-Feng
單位淡江大學電機工程學系
出版者Berlin, Heidelberg : Springer
著錄名稱、卷期、頁數Advances in Autonomous Robotics:
Joint Proceedings of the 13th Annual TAROS Conference and the 15th Annual FIRA RoboWorld Congress, pp.436-437
摘要This paper proposed an image processing system based on hardware accelerator design method in FPGA chip. The architectures of the image system will be described. A hardware accelerator for scaling image is designed with Avalon-MM burst mode in System-on-a-Programmable-Chip (SOPC). There is a human-machine interface which display on the LCD Touch Panel Module (LTM) is designed in the image processing system. A user can choose a scaling factor by touching screen panel, and then LTM will display a 640 × 480 image on the LTM screen. Finally, the experimental result shows the comparison of the two design methods, and the hardware accelerator has better performance than Nios II processor.
關鍵字FPGA; human-machine interface; hardware accelerator
語言英文
ISBN9783642325274
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