| An Efficient VLSI Architecture for Rivest-Shamir-Adleman Public-key Cryptosystem | |
|---|---|
| 學年 | 93 |
| 學期 | 1 |
| 出版（發表）日期 | 2004-12-01 |
| 作品名稱 | An Efficient VLSI Architecture for Rivest-Shamir-Adleman Public-key Cryptosystem |
| 作品名稱（其他語言） | |
| 著者 | 江正雄; Chiang, Jen-shiun; 簡丞志; Chien, Cheng-chih; Chen, Jian-kao; 周信國; Chou, Hsin-guo |
| 單位 | 淡江大學電機工程學系 |
| 出版者 | 臺北縣：淡江大學 |
| 著錄名稱、卷期、頁數 | 淡江理工學刊=Tamkang journal of science and engineering 7(4)，頁241-250 |
| 摘要 | In this paper, a new efficient VLSI architecture to compute modular exponentiation and modular multiplication for Rivest-Shamir-Adleman (RSA) public-key cryptosystem is proposed. We modify the conventional H-algorithm to find the modular exponentiation. By this modified H-algorithm, the modular multiplication steps for n-bit numbers are reduced by 5n/18 times. For the modular multiplication a modified L-algorithm (LSB first) is used. In the architecture of the modified modular multiplication the iteration times are only half of Montgomery's algorithm and the H-algorithm. The proposed architecture for the RSA public-key crypto-system has a data rate of 146 kb/s for 512-b words with a 200-MHz clock rate. |
| 關鍵字 | Data Security;H-algorithm;L-algorithm;Modular Exponentiation;Modular Multiplication;Montgomery's Algorithm;Public-key Cryptosystem;RSA;VLSI |
| 語言 | en |
| ISSN | 1560-6686 |
| 期刊性質 | 國內 |
| 收錄於 | |
| 產學合作 | |
| 通訊作者 | |
| 審稿制度 | 否 |
| 國別 | TWN |
| 公開徵稿 | |
| 出版型式 | ,電子版 |
| 相關連結 |
機構典藏連結 ( http://tkuir.lib.tku.edu.tw:8080/dspace/handle/987654321/52822 ) |
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