A Radix-2 Non-Restoring 32-b/32-b Ring Divider with Asynchronous Control Scheme
學年 87
學期 2
出版(發表)日期 1999-06-01
作品名稱 A Radix-2 Non-Restoring 32-b/32-b Ring Divider with Asynchronous Control Scheme
著者 江正雄; Chiang, Jen-shiun; 賴友仁; Lai, Eugene; Liao, Jun-yao
單位 淡江大學電機工程學系
出版者 淡江大學
著錄名稱、卷期、頁數 淡江理工學刊=Tamkang journal of science and engineering 2(1), pp.37-44
摘要 Division operation is very important in the computer system. Nowadays people use a hardware module─divider to implement the division algorithm. Conventionally synchronous techniques are applied to implement the divider. The synchronous systems always need system clock signals to trigger the system. However, the system clock of the synchronous system may cause some problems, such as clock skew, dynamic power consumption, ..., etc. Compared to synchronous systems, asynchronous circuits do not need system clock signals and thus the asynchronous system does not have the shortcomings mentioned above. Here we will propose a new asynchronous architecture for the divider. In this asynchronous scheme, the architecture is of simplicity and is very easy for the VLSI implementation. By this asynchronous architecture, we use TSMC’s 0.6um SPDM process to design a 32-b/32-b radix-2 non-restoring divider and the spice simulation proves it works. The HSPICE simulation shows that it can finish a 32-b/32-b division in between 3.7ns to 160.2ns.
關鍵字 Asynchronous circuits;conditional carry-selection adder;divider;radix-2 non-restoring division algorithm;synchronous circuits;VLSI
語言 en_US
ISSN 1560-6686
期刊性質 國內
國別 TWN
出版型式 ,紙本

機構典藏連結 ( http://tkuir.lib.tku.edu.tw:8080/dspace/handle/987654321/46128 )