| Built-In Reseeding With Modifying Technique For Bist | |
|---|---|
| 學年 | 92 |
| 學期 | 2 |
| 出版（發表）日期 | 2004-05-01 |
| 作品名稱 | Built-In Reseeding With Modifying Technique For Bist |
| 作品名稱（其他語言） | |
| 著者 | Rau, Jiann-chyi; Yang, Ta-wei; Ho, Ying-fu |
| 單位 | 淡江大學電機工程學系 |
| 出版者 | World Scientific and Engineering Academy and Society (WSEAS) |
| 著錄名稱、卷期、頁數 | WSEAS Transactions on Circuits and System 3(3), pp.723-726 |
| 摘要 | During built-in self-test (BIST), the set of patterns generated by a pseudo-random patterns generator may not provide a sufficiently high fault coverage and many patterns was undetected fault so some patterns not make test time can decrease. In this paper, we reseed and modify the pseudo-random bit to improve test length and achieve fault coverage of 100%. The fact that a random test set contains useless (non fault dropping) patterns, so we use parallel technology, including both reseeding and bit modifying (also called pattern mapping) to remove useless patterns (i.e. reduce the test time), leading to very short test length. The technique we present is applicable for single-stuck-at faults. Experimental results indicate that complete fault coverage-100% can be obtained with decrease test time. |
| 關鍵字 | BIST;pseudo-random patterns;reseed and modify;test length;single-stuck-at faults;fault coverage |
| 語言 | en |
| ISSN | 1109-2734 |
| 期刊性質 | 國外 |
| 收錄於 | |
| 產學合作 | |
| 通訊作者 | |
| 審稿制度 | 否 |
| 國別 | GRC |
| 公開徵稿 | |
| 出版型式 | ,紙本 |
| 相關連結 |
機構典藏連結 ( http://tkuir.lib.tku.edu.tw:8080/dspace/handle/987654321/46281 ) |
| SDGS | 產業創新與基礎設施 |
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