教師資料查詢 | 類別: 期刊論文 | 教師: 饒建奇JIANN-CHYI RAU (瀏覽個人網頁)

標題:Built-In Reseeding With Modifying Technique For Bist
學年92
學期2
出版(發表)日期2004/05/01
作品名稱Built-In Reseeding With Modifying Technique For Bist
作品名稱(其他語言)
著者Rau, Jiann-chyi; Yang, Ta-wei; Ho, Ying-fu
單位淡江大學電機工程學系
出版者World Scientific and Engineering Academy and Society (WSEAS)
著錄名稱、卷期、頁數WSEAS Transactions on Circuits and System 3(3), pp.723-726
摘要During built-in self-test (BIST), the set of patterns generated by a pseudo-random patterns generator may not provide a sufficiently high fault coverage and many patterns was undetected fault so some patterns not make test time can decrease. In this paper, we reseed and modify the pseudo-random bit to improve test length and achieve fault coverage of 100%. The fact that a random test set contains useless (non fault dropping) patterns, so we use parallel technology, including both reseeding and bit modifying (also called pattern mapping) to remove useless patterns (i.e. reduce the test time), leading to very short test length. The technique we present is applicable for single-stuck-at faults. Experimental results indicate that complete fault coverage-100% can be obtained with decrease test time.
關鍵字BIST;pseudo-random patterns;reseed and modify;test length;single-stuck-at faults;fault coverage
語言英文
ISSN1109-2734
期刊性質國外
收錄於
產學合作
通訊作者
審稿制度
國別希臘
公開徵稿
出版型式,紙本
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