Concurrent bit-plane coding architecture for EBCOT in JPEG2000
學年 94
學期 2
發表日期 2006-05-21
作品名稱 Concurrent bit-plane coding architecture for EBCOT in JPEG2000
作品名稱（其他語言）
著者 Chiang, Jen-shiun; Hsieh, Chang-yo; Liu, Jin-chan; Chien, Cheng-chih
作品所屬單位 淡江大學電機工程學系
出版者 Institute of electrical and electronics engineers (IEEE)
會議名稱 Circuits and Systems, 2006. ISCAS 2006. Proceedings. 2006 IEEE International Symposium on
會議地點 Island of Kos, Greek
摘要 This work presents a concurrent bit-plane coding architecture for EBCOT of JPEG2000. The architecture uses two bit-planes at the same time to encode data and this scheme can reduce the requirement of internal memory efficiently. Compared with the conventional approach, our concurrent architecture can save 8K-bit internal memory. In our proposed architecture, it can process data as long as the data of the two bit-planes are available, and at the same time the system can keep reading data from the external memory. This approach can increase the computation efficiency and avoid the waiting time for reading external data. It can also reduce the access times of the internal memory. Compared with the conventional context modeling architecture, the proposed concurrent bit-plane coding architecture can reduce the computation time by more than 50%
關鍵字
語言 en
收錄於
會議性質 國際
校內研討會地點
研討會時間 20060521~20060524
通訊作者
國別 GRC
公開徵稿 Y
出版型式
出處 Circuits and Systems, 2006. ISCAS 2006. Proceedings. 2006 IEEE International Symposium on, pp.4595-4598
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