A synthesizable pseudo fractional-N clock generator with improved duty cycle output
學年 100
學期 1
出版（發表）日期 2011-10-01
作品名稱 A synthesizable pseudo fractional-N clock generator with improved duty cycle output
作品名稱（其他語言）
著者 Yang, Wei-Bin; Hsieh, Chang-Yo
單位 淡江大學電機工程學系
出版者 London: Elsevier Ltd
著錄名稱、卷期、頁數 Microelectronics Journal 42(10), pp.1099-1106
摘要 A proposed synthesizable pseudo fractional-N clock generator with improved duty cycle output is presented by the pseudo fractional-N frequency synthesizer unit for SoC chips and the dynamic frequency scaling applications. The different clock frequencies can be generated by following the design flowchart. It has been fabricated in a 0.13 μm CMOS technology and work with a supply voltage of 1.2 V. According to measured results, the frequency range of the proposed synthesizable pseudo fractional-N clock generator is from 12.5 MHz to 1 GHz and the peak-to-peak jitter is less than 5% of the output period. Duty cycle error rate of the output clock frequency is 1.5% and the measured power dissipation of the pseudo fractional-N frequency synthesizer unit is 146 μW at 304 MHz.
關鍵字 Synthesizable; Clock generator; Pseudo fractional-N; Duty cycle
語言 en_US
ISSN 0026-2692
期刊性質 國外
收錄於 SCI
產學合作
通訊作者 Ynag, Wei-Bin
審稿制度
國別 GBR
公開徵稿
出版型式 紙本
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