教師資料查詢 | 類別: 會議論文 | 教師: 江正雄 CHIANG JEN-SHIUN (瀏覽個人網頁)

標題:The Design and Implementation of a 3.3V 400MHz All Digital Phase-Locked Loop
學年
學期
發表日期1997/08/21
作品名稱The Design and Implementation of a 3.3V 400MHz All Digital Phase-Locked Loop
作品名稱(其他語言)
著者Chen, Kuang-Yuan; Chiang, Jen-Shiun
作品所屬單位淡江大學電機工程學系
出版者
會議名稱第八屆超大型積體電路設計暨計算機輔助設計技術研討會=The 8th VLSI Design/CAD Symposium
會議地點南投縣, 臺灣
摘要This paper is to design and implement an all digital phase-locked loop (ADPLL) circuit. The core of the ADPLL is the switch-tuning digital control oscillator (DCO). Our design of the DCO has features of small hardware cost. This ADPLL has characteristics of fast frequency locking, full digitization, easy design and implementation, and good stability. It is suitable to be used as the clock generator for high performance microprocessors. A prototype of this ADPLL chip is designed and implemented by TSMC's 0.6um SPDM CMOS process. The simulation shows that this chip can operate in the range between 60MHz and 400MHz, and operates at 4x the reference clock frequency. The phase lock process is 47 clock cycles, and the phase error is less than 0.1ns. The chip consists of 4026 MOS transistors and the core size of the VLSI layout is 923.mu.m*921.mu.m.
關鍵字全數位;鎖相迴路;電路設計;數位控制振盪器;頻率比較器;相位偵測器;All Digital;Phase Locked Loop;Circuit Design;Digital Control Oscillator;Frequency Comparator;Phase Detector
語言英文
收錄於
會議性質國內
校內研討會地點
研討會時間19970821~19970823
通訊作者
國別中華民國
公開徵稿Y
出版型式紙本
出處第八屆超大型積體電路設計暨計算機輔助設計技術研討會論文集(VLSICAD)=Proceedings of the 8th VLSI Design/CAD Symposium頁173-176
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