A Fast Sequential MRU Cache with Competitive Hardware Cost
學年 89
學期 2
發表日期 2001-07-09
作品名稱 A Fast Sequential MRU Cache with Competitive Hardware Cost
作品名稱(其他語言)
著者 Chen, Hsin-Chuan; Chiang, Jen-Shiun; Lin, Yu-Sen
作品所屬單位 淡江大學電機工程學系
出版者
會議名稱 第二屆國際平行與分散式計算機應用及技術會議=The Second International Conference on Parallel and Distributed Computing,Applications,and Technologies
會議地點 臺北縣, 臺灣
摘要 The tradeoff between direct-mapped caches and set-associative cachesis an important issue in the research on the performance of caches.The set-associative caches with higher associativity provide lowermiss rate, however, they suffer from longer hit access time. MRU (mostrecently used) cache is one of the set-associative caches that addressimplementation of associativity higher than two. However, the accesstime is increased because the MRU information must be fetched beforeaccessing the MRU cache. In this paper, we propose a hardware schemethat separately divides tag memory and data memory into n banksassociated with two multiplexors to reduce the sequential search time.Applying this approach to the access organization of an MRU cache canimprove the access time of the sequential MRU cache. Furthermore, thefirst hit access time of the proposed architecture is almost equal tothat of the MRU cache with parallel search, but the hardwarecomplexity is less than that of the parallel search MRU cache. Theproposed hardware scheme provides an excellent average access timewhen the associativity is 4-way, and it could be applied to parallelarchitectures, such as the multiprocessor system, to increase theoverall system performance.
關鍵字 目前最常使用快取;集合關聯式快取;平均存取時間;硬體成本;平行架構;Most Recently Used Cache;Set Associative Cache;Average Access Time;Hardware Cost;Parallel Architecture
語言 en
收錄於
會議性質 國際
校內研討會地點 淡水校園
研討會時間 20010709~20010711
通訊作者
國別 TWN
公開徵稿 Y
出版型式 紙本
出處 第二屆國際平行與分散式計算機應用及技術會議論文集=Proceedings,The Second International Conference on Parallel and Distributed Computing,Applications,and Technologies,頁220-227
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