教師資料查詢 | 類別: 會議論文 | 教師: 江正雄CHIANG JEN-SHIUN (瀏覽個人網頁)

標題:An Efficient VLSI Architecture for 2-D DWT using Lifting Scheme
學年93
學期2
發表日期2005/04/28
作品名稱An Efficient VLSI Architecture for 2-D DWT using Lifting Scheme
作品名稱(其他語言)
著者Chiang, Jen-Shiun; Hsia, Chih-Hsien
作品所屬單位淡江大學電機工程學系
出版者
會議名稱2005年國際系統與信號研討會=2005 International Conference on System & Signals (ICSS2005)
會議地點高雄, 臺灣
摘要In this paper, we propose a highly efficient VLSI architecture for 2-D lifting-based 5/3 filter discrete wavelet transform (DWT). The architecture is based on the pipelined and folding scheme processing to achieve near 100% hardware utilization ratio and reduce the silicon area. The advantages of the proposed DWT have the characteristics of higher hardware utilization, less memory requirement, and regular data flow. It is suitable for VLSI implementation and can be applied to real-time operating of JPEG2000 and MPEG4 applications.
關鍵字
語言英文
收錄於
會議性質國際
校內研討會地點
研討會時間20050428~20050429
通訊作者
國別中華民國
公開徵稿Y
出版型式紙本
出處2005年國際系統與信號研討會論文集=Proceedings of 2005 International Conference on System & Signals (ICSS2005),4頁
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