Memory-efficient architecture of 2-D lifting-based discrete wavelet transform
學年 99
學期 2
出版（發表）日期 2011-07-01
作品名稱 Memory-efficient architecture of 2-D lifting-based discrete wavelet transform
作品名稱（其他語言）
著者 Hsia, Chih-Hsien; Li, Wei-Ming; Chiang, Jen-Shiun
單位 淡江大學電機工程學系
出版者 Abingdon: Taylor & Francis Ltd.
著錄名稱、卷期、頁數 Journal of the Chinese Institute of Engineers=中國工程學刊 34(5), pp.629-643
摘要 This article presents new hardware architectures to address critical issues in 2-D dual-mode (supporting 5/3 lossless and 9/7 lossy coding modes) lifting-based discrete wavelet transform (LDWT) for Motion-JPEG2000. The massive requirement of transpose memory is the most critical for LDWT. The proposed architecture can support high-resolution videos and reduce the internal memory requirement significantly. In our LDWT approach, the signal flow is revised from row-wise only to mixed row- and column-wise, and a new architecture, called interlaced read scan architecture (IRSA), is used to reduce the transpose memory. By the IRSA approach, the transpose memory size is only 2N or 4N (5/3 or 9/7 mode) for an N × N DWT. Besides, the proposed 2-D LDWT operates with parallel and pipelined schemes to increase the operation speed. It can be applied to real-time visual operations such as JPEG2000 and Motion-JPEG2000.
關鍵字 lifting scheme; discrete wavelet transform (DWT); low internal memory; interlaced read scan architecture (IRSA)
語言 en
ISSN 0253-3839
期刊性質 國外
收錄於
產學合作
通訊作者 Hsia, Chih-Hsien
審稿制度
國別 GBR
公開徵稿
出版型式 紙本
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