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標題:Hardware Accelerator Design for Image Processing
學年101
學期1
發表日期2012/08/20
作品名稱Hardware Accelerator Design for Image Processing
作品名稱(其他語言)
著者Li, S.A.; Wong, C.C.; Yang, C.Y.; Chen, L.F.
作品所屬單位淡江大學電機工程學系
出版者Berlin: Springer Berlin Heidelberg
會議名稱Joint Proceedings of the 13th Annual TAROS Conference and the 15th Annual FIRA RoboWorld Congress
會議地點Bristol, UK
摘要This paper proposed an image processing system based on hardware accelerator design method in FPGA chip. The architectures of the image system will be described. A hardware accelerator for scaling image is designed with Avalon-MM burst mode in System-on-a-Programmable-Chip (SOPC). There is a human-machine interface which display on the LCD Touch Panel Module (LTM) is designed in the image processing system. A user can choose a scaling factor by touching screen panel, and then LTM will display a 640 × 480 image on the LTM screen. Finally, the experimental result shows the comparison of the two design methods, and the hardware accelerator has better performance than Nios II processor.
關鍵字FPGA; human-machine interface; hardware accelerator
語言英文
收錄於
會議性質國際
校內研討會地點
研討會時間20120820~20120823
通訊作者Shih-An Li
國別英國
公開徵稿Y
出版型式電子版;紙本
出處Lecture Notes in Computer Science 7429, pp.436-437
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