A new phase interpolator circuit for frequency multiplication design in embedded system
學年 101
學期 2
出版（發表）日期 2013-03-01
作品名稱 A new phase interpolator circuit for frequency multiplication design in embedded system
作品名稱（其他語言）
著者 Yang, Wei-Bin; Wang, Chi-Hsiung; Xie, Shao-Jyun
單位 淡江大學電機工程學系
出版者 Japan: ICIC International
著錄名稱、卷期、頁數 ICIC Express Letters 7(3A), pp.831-837
摘要 The new phase interpolator circuit is proposed to double the clock frequency up to 480MHz for USB application in embedded system. The most crucial purpose is ensuring that the interpolated signal rises precisely at one-half of time interval between two complementary signals. The proposed circuit was fabricated in a 0.35μm 1P2M complementary metal-oxide-semiconductor (CMOS) process and works with a supply voltage of 3.3V. By Hspice simulation result, the measured output frequency is 480MHz with 240MHz input clock frequency. The measured jitter performance and power consumption is 10.7ps and 2.6mW, respectively. Therefore, the proposed phase interpolator circuit can be applied to 480MHz USB devices.
關鍵字
語言 en
ISSN 1881-803X
期刊性質 國外
收錄於 EI
產學合作
通訊作者 Yang, Wei-Bin
審稿制度 是
國別 JPN
公開徵稿
出版型式 ,電子版
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機構典藏連結 ( http://tkuir.lib.tku.edu.tw:8080/dspace/handle/987654321/81309 )

機構典藏連結
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