教師資料查詢 | 類別: 會議論文 | 教師: 江正雄 CHIANG JEN-SHIUN (瀏覽個人網頁)

標題:Design of High-Efficiency Multimedia Signal Processing IP for 2-D DWT VLSI Architecture
學年
學期
發表日期2005/11/17
作品名稱Design of High-Efficiency Multimedia Signal Processing IP for 2-D DWT VLSI Architecture
作品名稱(其他語言)
著者Hsia, Chih-Hsien; Chiang, Jen-Shiun; Huang, Ting-Wei
作品所屬單位淡江大學電機工程學系
出版者雲林縣雲林科技大學
會議名稱2005民生電子暨信號處理研討會=Workshop on Consumer Electronics and Signal Processing
會議地點臺灣, 雲林縣
摘要This work presents novel algorithms and hardware architectures to improve the critical issue of 2-D discrete wavelet transform (DWT). On-chip memory cost is a very important problem in multimedia IC design. The architecture is based on the proposed interlaced read scan algorithm (IRSA) and pipeling scheme processing to achieve low-memory size and high-speed operation. The proposed lifting-based DWT architecture has the advantages of lower computational complexity. Meanwhile, our architecture can also provide embedded symmetric boundary extension function and regular data flow, and is suitable for VLSI implementation. It can be applied to real-time image/video operating of JPEG 2000 and MPEG-4 applications. A 2-D DWT VLSI test chip was designed and simulated by TSMC 0.35.mu. m 1P4M CMOS technology. The memory requirement of the N*N 2-D DWT is N and it can operate at 100MHz clock frequency.
關鍵字Discrete wavelet transform (DWT); Interlaced read scan algorithm(IRSA); Lifting-based DWT; Multiresolution; On-chip memory; Real-time
語言英文
收錄於
會議性質國內
校內研討會地點
研討會時間20051117~20051118
通訊作者
國別中華民國
公開徵稿
出版型式
出處2005民生電子暨信號處理研討會論文集;Proceedings of Workshop on Consumer Electronics and Signal Processing, 6p.
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