The High-Performance and Low-Power CMOS Output Driver Design
學年 99
學期 2
發表日期 2011-06-20
作品名稱 The High-Performance and Low-Power CMOS Output Driver Design
作品名稱（其他語言）
著者 Yang, Wei-bin; Liao, Pei-hsuan; Wang, Chi-hsiung; Cheng, Ching-tsan
作品所屬單位 淡江大學電機工程學系
出版者 Nanchang University; Springer; IEEE IAS Nanchang Chapter
會議名稱
會議地點
摘要 There are many important points for high-speed CMOS integrated circuit, such as switching speed, power dissipation and full-swing of voltage. In this paper, a group of high performance and low-power bootstrapped CMOS drivers are designed in order to reduce power consumption and enhance the speed of switch for driving a large load, where the drivers will reduce the power consumption by using bootstrap manipulate conditional to input statistics. Moreover, the low swing bootstrapped feedback controlled split path (LBFS) is conducted to reduce the dynamic power dissipation and limiting the voltage swing of gate of the output stage. Finally, the charge transfer feedback controlled split path (CRFS) CMOS buffer is used to restitute and pull down the gate voltage for reducing power consumption and line noise. According to the HSPICE simulation results, the proposed drivers of the CMOS driver are reduced by 20%~40 compared to the conventional design.
關鍵字
語言 en
收錄於
會議性質 國際
校內研討會地點
研討會時間 20110620~20110622
通訊作者
國別
公開徵稿
出版型式
出處 2011 International Conference on Electric and Electronics (EEIC 2011), Nanchang, China
相關連結

機構典藏連結 ( http://tkuir.lib.tku.edu.tw:8080/dspace/handle/987654321/75307 )

機構典藏連結
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