A 400 MHz 0.934ps rms Jitter Multiplying Delay Lock Loop in 90-nm CMOS Process
學年 99
學期 1
發表日期 2010-12-12
作品名稱 A 400 MHz 0.934ps rms Jitter Multiplying Delay Lock Loop in 90-nm CMOS Process
作品名稱（其他語言）
著者 施鴻源; 陳秋榜
作品所屬單位 淡江大學電機工程學系
出版者 USA:Institute of Electrical and Electronics Engineers
會議名稱
會議地點 Athens, Greece
摘要 A multiplying delay-locked loop (MDLL) is adopted for low-jitter clock generation. This architecture overcomes the drawback of phase-locked loops (PLL) such as jitter accumulation, and maintain the advantage of a PLL for multirate frequency multiplication. The MDLL, implemented in 90-nm CMOS technology, occupies about 1 mm2 and works at 400 MHz with multiplication ratio of 4. The complete synthesizer, including the output buffers, dissipates 31 mW from a 1.2V supply at 400 MHz. The rms jitter is 0.934 ps according to the phase noise integrated from 1 KHz to 1 MHz, when the output frequency is 400 MHz.
關鍵字 Low-Jitter;MDLL
語言 en
收錄於
會議性質 國際
校內研討會地點
研討會時間
通訊作者
國別
公開徵稿
出版型式
出處 The 17th IEEE International Conference on Electronics, Circuits, and Systems (ICECS 2010),pp.53-56
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