| Design of Dynamically Assignmentable TAM Width for Testing Core-Based SOCs | |
|---|---|
| 學年 | 95 |
| 學期 | 1 |
| 發表日期 | 2006-12-04 |
| 作品名稱 | Design of Dynamically Assignmentable TAM Width for Testing Core-Based SOCs |
| 作品名稱（其他語言） | |
| 著者 | Rau, Jiann-Chyi; Chen, Chien-Shiun; Wu, Po-Han |
| 作品所屬單位 | 淡江大學電機工程學系 |
| 出版者 | |
| 會議名稱 | Circuits and Systems, 2006. APCCAS 2006. IEEE Asia Pacific Conference on |
| 會議地點 | Singapore |
| 摘要 | Test access mechanism (TAM) and testing schedule for system-on-chip (SOC) are challenging problems. Testing schedule must be effective to minimize testing time, under the constraint of test resources. This paper presents a new method based on generalized rectangle packing, as two-dimensional packing. A core cuts into many pieces and utilizes the design of reconfigurable core wrappers, and is dynamic to change the width of the TAM executing the core test. Therefore, a core can utilize different TAM width to complete test |
| 關鍵字 | SOC Testing;TAM;Testing Scheduling |
| 語言 | en |
| 收錄於 | |
| 會議性質 | 國際 |
| 校內研討會地點 | |
| 研討會時間 | 20061204~20061207 |
| 通訊作者 | |
| 國別 | SGP |
| 公開徵稿 | Y |
| 出版型式 | |
| 出處 | Circuits and Systems, 2006. APCCAS 2006. IEEE Asia Pacific Conference on, pp.1399-1402 |
| 相關連結 |
機構典藏連結 ( http://tkuir.lib.tku.edu.tw:8080/dspace/handle/987654321/70367 ) |
| SDGS | 產業創新與基礎設施 |
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