Multi-Chains Encoding Scheme in Low-Cost ATE
學年 98
學期 2
發表日期 2010-05-30
作品名稱 Multi-Chains Encoding Scheme in Low-Cost ATE
作品名稱（其他語言）
著者 饒建奇; Rau, Jiann-Chyi; Chen, Gong-Han; Wu, Po-Han
作品所屬單位 淡江大學電機工程學系
出版者 IEEE
會議名稱 Circuits and Systems (ISCAS), Proceedings of 2010 IEEE International Symposium on
會議地點 Paris, France
摘要 Generally speaking, the dependency data compression is very useful for Intellectual Property (IP) cores and SoC. We consider the shift-in power and compression ratio in low-cost ATE environment. We propose new compression architecture with fixed length for running ones. We suppose that the ATE has not repeated function and synchronization signal. In the results, when the complexity of VLSI circuit is growing up, the number of input pins for testing is very low. The average compression ratio of our method is 63% for MinTest on ISCAS'89 benchmarks. The average of peak/WTC shift-in turns to 3×/6.6×, after comparing Selective Scan Slice (SSS) and our method. The average of hardware overhead is 6%.
關鍵字
語言
收錄於
會議性質 國際
校內研討會地點
研討會時間 20100530~20100602
通訊作者
國別 FRA
公開徵稿 Y
出版型式
出處 Circuits and Systems (ISCAS), Proceedings of 2010 IEEE International Symposium on, pp.1587-1590
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