教師資料查詢 | 類別: 會議論文 | 教師: 李鴻璋 Lee Hung-chang (瀏覽個人網頁)

標題:Multiprocessor architecture reconciling symbolic with numerical processing
學年
學期
發表日期1989/05/17
作品名稱Multiprocessor architecture reconciling symbolic with numerical processing
作品名稱(其他語言)
著者Jang, G. S. ; Lai, F. ; 李鴻璋; Lee, H. C. ; Maa, Y. C. ; Parng, T. M. ; Tsai, J. Y.
作品所屬單位淡江大學資訊管理學系
出版者IEEE
會議名稱International symposium on VLSI technology, system and applications
會議地點Taipei, Taiwan
摘要The design of CPU (central processing unit) chips for the MARS project is described. They are the IFU (instruction fetch unit), IPU (integer processing unit), and LPU (list processing unit). The IFU is devised to interleave instruction fetch and execution, and thus to achieve coordinated execution among datapath chips. The IPU is the main computing engine for integer operations and operand address calculation. By using dual-instruction buffers, a reserved phase for branch/jump target fetch, and instruction decode peeping, the architecture can support almost-zero-delay branching and super-zero-delay jump. The LPU handles a Lisp runtime environment, dynamic type checking, and fast list access. In this architecture, the critical path of complex register file access and ALU operation is distributed over the LPU and IPU, and list tracing can be executed quickly by the nondelayed car or cdr instructions.
關鍵字
語言英文
收錄於
會議性質國內
校內研討會地點
研討會時間19890517~19890519
通訊作者
國別中華民國
公開徵稿Y
出版型式紙本
出處International symposium on VLSI technology, system and applications, pp.365-370
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