Multiprocessor architecture reconciling symbolic with numerical processing
學年 77
學期 2
發表日期 1989-05-17
作品名稱 Multiprocessor architecture reconciling symbolic with numerical processing
作品名稱（其他語言）
著者 Jang, G. S. ; Lai, F. ; 李鴻璋; Lee, H. C. ; Maa, Y. C. ; Parng, T. M. ; Tsai, J. Y.
作品所屬單位 淡江大學資訊管理學系
出版者 IEEE
會議名稱 International symposium on VLSI technology, system and applications
會議地點 Taipei, Taiwan
摘要 The design of CPU (central processing unit) chips for the MARS project is described. They are the IFU (instruction fetch unit), IPU (integer processing unit), and LPU (list processing unit). The IFU is devised to interleave instruction fetch and execution, and thus to achieve coordinated execution among datapath chips. The IPU is the main computing engine for integer operations and operand address calculation. By using dual-instruction buffers, a reserved phase for branch/jump target fetch, and instruction decode peeping, the architecture can support almost-zero-delay branching and super-zero-delay jump. The LPU handles a Lisp runtime environment, dynamic type checking, and fast list access. In this architecture, the critical path of complex register file access and ALU operation is distributed over the LPU and IPU, and list tracing can be executed quickly by the nondelayed car or cdr instructions.
關鍵字
語言 en
收錄於
會議性質 國內
校內研討會地點
研討會時間 19890517~19890519
通訊作者
國別 TWN
公開徵稿 Y
出版型式 紙本
出處 International symposium on VLSI technology, system and applications, pp.365-370
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