| Optimization on instruction reorganization | |
|---|---|
| 學年 | 79 |
| 學期 | 1 |
| 發表日期 | 1990-11-27 |
| 作品名稱 | Optimization on instruction reorganization |
| 作品名稱（其他語言） | |
| 著者 | Lai, F. ; 李鴻璋; Lee, H. C. ; Lee, C. L. |
| 作品所屬單位 | 淡江大學資訊管理學系 |
| 出版者 | IEEE |
| 會議名稱 | 1990 ACM & IEEE the 23rd international symposium and workshop on Microprogramming and Microarchitecture(Micro-23) |
| 會議地點 | Orlando, Florida, USA |
| 摘要 | A pipelined processor increases its performance by partitioning an instruction into several separate operation steps. Several instructions can be executed in the pipeline in different pipe stages at the same time. Because of the overlapped execution of instructions, the result of an instruction may be used before it is available. One way to solve this problem is to schedule instructions at compiler time, thus the codes generated will be free from interlocks. The scheduling algorithm presented by T. Gross (1983) and J. Hennessy and T. Gross (1983) had significantly reduced the pipeline interlocks. With some modifications to distinguish the conflict condition, the algorithm does better at the same cost. |
| 關鍵字 | |
| 語言 | en |
| 收錄於 | |
| 會議性質 | 國內 |
| 校內研討會地點 | |
| 研討會時間 | 19901127~19901129 |
| 通訊作者 | |
| 國別 | USA |
| 公開徵稿 | Y |
| 出版型式 | 紙本 |
| 出處 | 1990 ACM & IEEE the 23rd international symposium and workshop on Microprogramming and Microarchitecture(Micro-23), pp.143-148 |
| 相關連結 |
機構典藏連結 ( http://tkuir.lib.tku.edu.tw:8080/dspace/handle/987654321/68451 ) |
GoogleAnalytics