| MARS: aRISC-based architecture for Lisp | |
|---|---|
| 學年 | 78 |
| 學期 | 2 |
| 出版（發表）日期 | 1990-03-01 |
| 作品名稱 | MARS: aRISC-based architecture for Lisp |
| 作品名稱（其他語言） | |
| 著者 | Lee, Hung-Chang; Lai, Feipei; Tsai, Jenn-yuan; Parng, Tai-ming |
| 單位 | 淡江大學資訊管理學系 |
| 出版者 | Oxford: Pergamon |
| 著錄名稱、卷期、頁數 | Engineering Applications of Artificial Intelligence 3(1), pp.19-29 |
| 摘要 | A RISC-based chip set architecture for Lisp is presented in this paper. This architecture contains an instruction fetch unit (IFU) and three processing units—integer processing unit (IPU), floating-point processing unit (FPU), and list processing unit (LPU). The IFU feeds instructions to the processing units and supports fast procedure call/return and branch, the IPU and FPU execute operations of different data type, and the LPU handles the Lisp runtime environment, dynamic type checking, and fast list access. In this architecture, the critical path of complex register file access and ALU operation is distributed into the LPU and IPU, and the tracing of a list can be done quickly by the non-delayed car or cdr instructions of the LPU. Performance simulation shows that this architecture would be about 6.2 times faster than SPUR and about 2.2 times faster than MIPS-X. |
| 關鍵字 | LISP; reduced instruction set computing; special purpose computers |
| 語言 | en |
| ISSN | 0952-1976 1873-6769 |
| 期刊性質 | 國外 |
| 收錄於 | |
| 產學合作 | |
| 通訊作者 | |
| 審稿制度 | |
| 國別 | GBR |
| 公開徵稿 | |
| 出版型式 | 紙本 電子版 |
| 相關連結 |
機構典藏連結 ( http://tkuir.lib.tku.edu.tw:8080/dspace/handle/987654321/68601 ) |
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