| An Efficient Algorithm to Selectively Gate Scan Cells for Capture Power Reduction | |
|---|---|
| 學年 | 99 |
| 學期 | 2 |
| 出版（發表）日期 | 2011-03-01 |
| 作品名稱 | An Efficient Algorithm to Selectively Gate Scan Cells for Capture Power Reduction |
| 作品名稱（其他語言） | |
| 著者 | Rau, Jiann-Chyi; Wu, Chung-Lin; Wu, Po-Han |
| 單位 | 淡江大學電機工程學系 |
| 出版者 | 新北市：淡江大學 |
| 著錄名稱、卷期、頁數 | Tamkang Journal of Science and Engineering=淡江理工學刊 14(1), pp.39-48 |
| 摘要 | Recently, power dissipation in full-scan testing has brought a great challenge for test engineers. In addition to shift power reduction, excessive switching activity during capture operation may lead to circuit malfunction and yield loss. In this paper, a new algorithm is proposed with using clock gating technique on a part of the scan cells to prevent the internal circuit from unnecessary transitions. These scan cells are divided into several exclusive scan groups. For each test vector, only a portion of the scan groups are activated to store the test response per capture cycle. The proposed method can reduce the capture power dissipation without any influence on fault coverage or testing time. Experimental results for ISCAS'89 benchmark circuits show that the capture power reduction in test sequence can up to 55%. |
| 關鍵字 | Clock Gating;Scan Test;Low Power Scan Test;Full-Scan Testing;Design for Testability;Yield Loss |
| 語言 | en |
| ISSN | 1560-6686 |
| 期刊性質 | 國內 |
| 收錄於 | EI |
| 產學合作 | |
| 通訊作者 | Rau, Jiann-Chyi |
| 審稿制度 | 否 |
| 國別 | TWN |
| 公開徵稿 | |
| 出版型式 | ,電子版,紙本 |
| 相關連結 |
機構典藏連結 ( http://tkuir.lib.tku.edu.tw:8080/dspace/handle/987654321/61038 ) |
| SDGS | 產業創新與基礎設施 |
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