教師資料查詢 | 類別: 期刊論文 | 教師: 饒建奇JIANN-CHYI RAU (瀏覽個人網頁)

標題:The Efficient TAM Design for Core-Based SOCs Testing
學年97
學期1
出版(發表)日期2008/11/01
作品名稱The Efficient TAM Design for Core-Based SOCs Testing
作品名稱(其他語言)
著者Rau, Jiann-chyi; Wu, Po-han; Chien, Chih-lung; Wu, Chien-hsu
單位淡江大學電機工程學系
出版者Athens: World Scientific and Engineering Academy and Society (W S E A S)
著錄名稱、卷期、頁數WSEAS Transactions on Circuits And Systems 11(7), pp.922-931
摘要This paper presents a framework and an efficient method to determine SOC test schedules. We increase the test TAM widths by the framework. Our method deals with the traditional scan chains and reconfigurable multiple scan chains. Experimental results for ITC’02 SOC TEST Benchmarks show that we obtain better test application time when compared to previously published algorithms. Test access mechanism (TAM) and test schedule for System-On-chip (SOC) are challenging problems. Test schedule must be effective to minimize testing time, under the constraint of test resources. This paper presents a core section method based on generalized 2-D rectangle packing. A core cuts into many pieces and utilizes the design of reconfigurable core wrappers, and is dynamic to change the width of the TAM executing the core test. Therefore, a core can utilize different TAM width to complete test.
關鍵字SOC Testing;TAM;Testing Scheduling
語言英文
ISSN1109-2734
期刊性質
收錄於EI
產學合作
通訊作者
審稿制度國外
國別希臘
公開徵稿
出版型式紙本
相關連結
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