教師資料查詢 | 類別: 期刊論文 | 教師: 江正雄CHIANG JEN-SHIUN (瀏覽個人網頁)

標題:A low-jitter phase-interpolation DDS using dual-slope integration
學年93
學期1
出版(發表)日期2004/09/25
作品名稱A low-jitter phase-interpolation DDS using dual-slope integration
作品名稱(其他語言)
著者Chen, Hsin-chuan; 江正雄; Chiang, Jen-shiun
單位淡江大學電機工程學系
出版者
著錄名稱、卷期、頁數IEICE Electronics Express 1(12), pp.333-338
摘要In this paper, a new phase-interpolation DDS scheme is proposed, which uses the output of the phase accumulator to provide positive-slope integration on an integration capacitor in the first phase, and then performs negative-slope integration operation on the same integration capacitor in the second phase. By using dual-slope integration on a single capacitor, the delay time error caused by capacitance error can be avoided and the die size can be reduced in circuit implementation. Therefore, the proposed DDS without ROM tables can achieve a low-jitter clock output due to generating the more precise delay time.
關鍵字phase-interpolation DDS;dual-slope integration;capacitance error;delay time error
語言英文(美國)
ISSN1349-2543
期刊性質國外
收錄於
產學合作
通訊作者
審稿制度
國別日本
公開徵稿
出版型式,電子版
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