| Table-lookup approach for compiling two-level data-processor mappings in HPF | |
|---|---|
| 學年 | 86 |
| 學期 | 1 |
| 出版（發表）日期 | 1998-01-01 |
| 作品名稱 | Table-lookup approach for compiling two-level data-processor mappings in HPF |
| 作品名稱（其他語言） | |
| 著者 | Shih, Kuei-ping; 石貴平 |
| 單位 | 淡江大學資訊工程學系 |
| 出版者 | Springer-Verlag |
| 著錄名稱、卷期、頁數 | Lecture notes in computer science 1366, p.34-48 |
| 摘要 | This paper presents some compilation techniques to compress holes. Holes are the memory locations mapped by useless template cells and are caused by the non-unit alignment stride in a two-level dataprocessor mapping. In a two-level data-processor mapping, there is a repeated pattern for array elements mapped onto processors. We classify blocks into classes and use a class table to record the attributes of classes for the data distribution. Similarly, data distribution on a processor also has a repeated pattern. We use compression table to record the attributes of the first data distribution pattern on that processor. By using class table and compression table, hole compression can be easily and efficiently achieved. Compressing holes can save memory usage, improve spatial locality and further increase system performance. The proposed method is efficient, stable and easy implement. The experimental results do confirm the advantages of our proposed method over existing methods. |
| 關鍵字 | Active Element;Array Element;Array Statement;Virtual Processor;Local Array |
| 語言 | en |
| ISSN | 0302-9743 |
| 期刊性質 | 國外 |
| 收錄於 | |
| 產學合作 | |
| 通訊作者 | |
| 審稿制度 | 否 |
| 國別 | DEU |
| 公開徵稿 | |
| 出版型式 | ,電子版 |
| 相關連結 |
機構典藏連結 ( http://tkuir.lib.tku.edu.tw:8080/dspace/handle/987654321/59509 ) |
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