A timing-driven pseudo-exhaustive testing of VLSI circuits
學年 88
學期 2
發表日期 2000-05-28
作品名稱 A timing-driven pseudo-exhaustive testing of VLSI circuits
作品名稱（其他語言）
著者 Chang, S. C.; Rau, J. C.
作品所屬單位 淡江大學電機工程學系
出版者 Institute of Electrical and Electronics Engineers (IEEE)
會議名稱 Circuits and Systems, 2000. Proceedings. ISCAS 2000 Geneva. The 2000 IEEE International Symposium on
會議地點 Geneva, Switzerland
摘要 The object of this paper is to reduce the delay penalty of bypass storage cell (bsc) insertion for pseudo-exhaustive testing. We first propose a tight delay lower bound algorithm which estimates the minimum circuit delay for each node after bsc insertion. By understanding how the lower bound algorithm loses optimality, we can propose a bsc insertion heuristic which tries to insert bscs so that the final delay is as close to the lower bound as possible. Our experiments show that the results of our heuristic are either optimal because they are the same as the delay lower bounds or they are very close to the optimal solutions.
關鍵字
語言 en
收錄於
會議性質 國際
校內研討會地點
研討會時間 20000528~20000531
通訊作者
國別 CHE
公開徵稿
出版型式 紙本
出處 Circuits and Systems, 2000. Proceedings. ISCAS 2000 Geneva. The 2000 IEEE International Symposium on (Volume:2 ), pp.665-668
相關連結

機構典藏連結 ( http://tkuir.lib.tku.edu.tw:8080/dspace/handle/987654321/38935 )

機構典藏連結
SDGS 減少不平等