A novel reseeding mechanism for pseudo-random testing of VLSI circuits
學年 93
學期 2
發表日期 2005-05-23
作品名稱 A novel reseeding mechanism for pseudo-random testing of VLSI circuits
作品名稱（其他語言）
著者 Rau, Jiann-chyi; Ho, Ying-fu; Wu, Po-han
作品所屬單位 淡江大學電機工程學系
出版者 Institute of Electrical and Electronics Engineers (IEEE)
會議名稱 Circuits and Systems, 2005. ISCAS 2005. IEEE International Symposium on
會議地點 Kobe, Japan
摘要 During built-in self-test (BIST), the set of patterns generated by a pseudo-random pattern generator may not provide sufficiently high fault coverage and many patterns were undetected fault (useless patterns). In order to reduce the test time, we can remove useless patterns or change them to useful patterns (fault dropping). In this paper, we reseed, modify the pseudo-random, and use an additional bit counter to improve test length and achieve high fault coverage. The fact is that a random test set contains useless patterns, so we present a technique, including both reseeding and bit modifying to remove useless patterns or change them to useful patterns, and when the patterns change, we pick out the numbers with less bits, leading to very short test length. The technique we present is applicable for single-stuck-at faults. The seeds we use are deterministic so 100% fault coverage can be achieve.
關鍵字
語言 en
收錄於
會議性質 國際
校內研討會地點
研討會時間 20050523~20050526
通訊作者
國別 JPN
公開徵稿
出版型式 紙本
出處 Circuits and Systems, 2005. ISCAS 2005. IEEE International Symposium on (Volume:3 ), pp.2979-2982
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