New architecture for high throughput-rate real-time 2-D DCT and the VLSI design
學年 85
學期 1
發表日期 1996-09-23
作品名稱 New architecture for high throughput-rate real-time 2-D DCT and the VLSI design
作品名稱（其他語言）
著者 Chiang, Jen-shiun; Huang, Hsiang-chou
作品所屬單位 淡江大學電機工程學系
出版者 N.Y.: Institute of Electrical and Electronic Engineers (IEEE)
會議名稱 ASIC Conference and Exhibit, 1996. Ninth Annual IEEE International
會議地點 Rochester, NY, USA
摘要 The discrete cosine transform (DCT) has been widely used as the core of digital image and video signal compression. However, its computation is so intensive and is of great necessity to meet the requirement of high speed. In this paper, a new architecture for the VLSI design of 2-D DCT has been developed. This architecture contains the following features: (1) using the programmable logic array (PLA) to replace multipliers, (2) overlapped row-column operations and pipeline structure to reduce the total computation time, and (3) highly modular and regular structure for the efficient VLSI implementation. The architecture is implemented to a 8×8 2-D DCT. The circuit is designed by UMC's 0.8 μm spdm CMOS process and the cell library is provided by ITRI CCL. The simulation is shown that the speed of the data processing for this DCT is more than 50 MHz. It performs equivalently 800 million multiplication and accumulations per second
關鍵字
語言 en
收錄於
會議性質 國際
校內研討會地點
研討會時間 19960923~19960927
通訊作者
國別
公開徵稿 Y
出版型式 紙本
出處 ASIC Conference and Exhibit, 1996. Proceedings., Ninth Annual IEEE International, pp.219-222
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