期刊論文
| 學年 | 99 |
|---|---|
| 學期 | 1 |
| 出版（發表）日期 | 2011-01-01 |
| 作品名稱 | Power-aware multi-chains encoding scheme for system-on-a-chip in low-cost environment |
| 作品名稱（其他語言） | |
| 著者 | Rau, Jiann-Chyi; Wu, Po-Han |
| 單位 | 淡江大學電機工程學系 |
| 出版者 | Stevenage: The Institution of Engineering and Technology |
| 著錄名稱、卷期、頁數 | IET Computers & Digital Techniques 5(1), pp.25-35 |
| 摘要 | As the test data continues to grow quickly, test cost also increased. For the sake of decreasing the test cost, this study presents a new compression for large circuit, which is based on multiple scan-chains and unknown structure. The proposed method is targeted at intellectual property cores and system-on-a-chip. The authors consider the shift-in power and compression ratio in low-cost automatic test equipment (ATE) environment. A new compression architecture with fixed length for running ones is proposed. For the proposed method, the ATE has no repeated function and synchronisation signal. In the results, when the complexity of very large-scale integrated circuit is growing up, the number of input pins for testing is very low. The average compression ratio of our method is 63% for MinTest and TetraMAX on ISCAS'89 benchmarks. The average of peak/weight transition count shift-in turns to 3x/6.6x for MinTest and 2.3x/5.6x for TetraMAX, after comparing selective scan slice and the proposed method. The average of hardware overhead is 6% for MinTest and 6.5% for TetraMAX. |
| 關鍵字 | |
| 語言 | en |
| ISSN | 1751-8601 |
| 期刊性質 | 國外 |
| 收錄於 | SCI EI |
| 產學合作 | |
| 通訊作者 | Rau, Jiann-Chyi |
| 審稿制度 | 是 |
| 國別 | GBR |
| 公開徵稿 | |
| 出版型式 | 紙本 |
| 相關連結 |
機構典藏連結 ( http://tkuir.lib.tku.edu.tw:8080/dspace/handle/987654321/61042 ) |