期刊論文
| 學年 | 103 |
|---|---|
| 學期 | 2 |
| 出版（發表）日期 | 2015-06-01 |
| 作品名稱 | Design of a shift-and-add based hardware accelerator for color space conversion |
| 作品名稱（其他語言） | |
| 著者 | Li, Shih-An; Chen, Ching-Yi; Chen, Ching-Han |
| 單位 | 淡江大學電機工程學系 |
| 出版者 | Heidelberg: Springer |
| 著錄名稱、卷期、頁數 | Journal of Real-Time Image Processing 10(2), pp.193-206 |
| 摘要 | In this paper, a Nios II processor based hardware/software co-design architecture with high expandability and development flexibility is proposed. The architecture integrates a pipelined color space converter (CSC), hardware accelerator (HA), and a LCD touch module (LTM) HA, which facilitates a high-speed implementation of RGB to YCbCr color space conversion with a real-time image display. To avoid the inefficiency of CSC circuit architecture due to massive floating-point multiplication operations in the conversion formulae, a GA-based evolutionary technique is used to realize the fast multiplierless CSC hardware architecture. Meanwhile, a pipeline design method is further applied to enhance the maximum operating frequency in circuit design. As compared to the commonly used floating-point based CSC architecture, the pipelined CSC HA in this paper has excellent advantages of low-complexity and high speed. After the mechanism is integrated into a system-on-a-programmable-chip (SOPC), the maximum operating frequency reached 168.12 MHz. That is, in every 0.11 s, the color space conversion can process a 512 × 512 image. This excellent result is practical to the fast development of different kind of image/video processing systems. |
| 關鍵字 | Hardware/software co-design;Color space converter;Hardware accelerator;SOPC |
| 語言 | en |
| ISSN | 1861-8200;1861-8219 |
| 期刊性質 | 國外 |
| 收錄於 | SCI |
| 產學合作 | |
| 通訊作者 | Chen, Ching-Yi |
| 審稿制度 | 是 |
| 國別 | DEU |
| 公開徵稿 | |
| 出版型式 | ,電子版,紙本 |
| 相關連結 |
機構典藏連結 ( http://tkuir.lib.tku.edu.tw:8080/dspace/handle/987654321/92247 ) |