期刊論文
| 學年 | 90 |
|---|---|
| 學期 | 1 |
| 出版（發表）日期 | 2002-01-01 |
| 作品名稱 | Reducing Cache Conflicts by Multi-Level Cache Partitioning and Array Elements Mapping |
| 作品名稱（其他語言） | |
| 著者 | 張志勇; Chang, Chih-yung; Sheu, J.P.; Chen, H.C. |
| 單位 | 淡江大學資訊工程學系 |
| 出版者 | |
| 著錄名稱、卷期、頁數 | The Journal of Supercomputing 22, p.197-219 |
| 摘要 | The paper presents an algorithm to reduce cache conflicts and improve cache localities. The proposed algorithm analyzes unique locality reference space for each reference pattern, partitions the multi-level cache into several parts with different size, and then maps array data onto the scheduled cache positions such that cache conflicts can be eliminated. To reduce the memory overhead for mapping array variables onto partitioned cache, a greedy method for rearranging array variables in declared statement is also developed. In addition, we combine loop tiling and the proposed schemes for exploiting both temporal and spatial reuse opportunities. To demonstrate that our approach is effective at reducing the number of cache conflicts and exploiting cache localities, we use Atom as a tool to develop a simulator for simulation of the behavior of direct-mapping cache. Experimental results show that applying our cache partitioning scheme can largely reduce the cache conflicts and thus save program execution time in both one-level cache and multi-level cache hierarchies. |
| 關鍵字 | Partitioning algorithms;Information science;Computer science;Scheduling algorithm;Pattern analysis;Algorithm design and analysis;Round robin;Costs;Degradation;Cache memory |
| 語言 | en |
| ISSN | |
| 期刊性質 | 國外 |
| 收錄於 | |
| 產學合作 | |
| 通訊作者 | |
| 審稿制度 | 否 |
| 國別 | USA |
| 公開徵稿 | |
| 出版型式 | ,電子版 |
| 相關連結 |
機構典藏連結 ( http://tkuir.lib.tku.edu.tw:8080/dspace/handle/987654321/59960 ) |