Discrete-Time Delta-Sigma Modulator with Successively Approximating Register ADC Assisted Analog Feedback Technique | |
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學年 | 113 |
學期 | 1 |
出版(發表)日期 | 2024-09-12 |
作品名稱 | Discrete-Time Delta-Sigma Modulator with Successively Approximating Register ADC Assisted Analog Feedback Technique |
作品名稱(其他語言) | |
著者 | Hsin-Liang Chen; Hong-Ming Chiu; Hung-Chi Chang; Jen-Shiun Chiang |
單位 | |
出版者 | |
著錄名稱、卷期、頁數 | Circuits System Signal Process |
摘要 | This paper proposes a delta-sigma modulator (DSM) for audio band applications with low-area cost and high-resolution performance characteristics. The proposed circuit is implemented by discrete-time switched capacitor circuits. It employs an assisted 6-bit successive approximation register (SAR) analog-to-digital converter (ADC) as the quantizer. Most importantly, it combines and shares the resistive digital-to-analog (DAC) in DSM and SAR ADC. Therefore, it can achieve high-efficiency advantages and reduce the chip layout cost. After all, the chip area is only 0.096 mm2 by the 0.18 um 1P6M CMOS process. It achieves 96 dB dynamic range (DR), 83.1 dB signal to noise and distortion ratio (SNDR), and 93.4 dB signal to noise ratio (SNR) with 25 kHz signal bandwidth and oversampling ratio (OSR) of 64. This is a preview of subscription |
關鍵字 | Delta-sigma modulator;Successive approximation register;Analog to digital converter;Sharing digital to analog converter |
語言 | en_US |
ISSN | 1531-5878; 0278-081X |
期刊性質 | 國外 |
收錄於 | SCI Scopus |
產學合作 | |
通訊作者 | |
審稿制度 | 是 |
國別 | USA |
公開徵稿 | |
出版型式 | ,電子版 |
相關連結 |
機構典藏連結 ( http://tkuir.lib.tku.edu.tw:8080/dspace/handle/987654321/126203 ) |
SDGS | 優質教育 |