教師資料查詢 | 類別: 會議論文 | 教師: 張世豪 SHIH-HAO CHANG (瀏覽個人網頁)

標題:An efficient VLSI architecture for 2-D dual-mode SMDWT
學年101
學期2
發表日期2013/04/10
作品名稱An efficient VLSI architecture for 2-D dual-mode SMDWT
作品名稱(其他語言)
著者Chih-Hsien Hsia;Jen-Shiun Chiang;Shih-Hao Chang
作品所屬單位
出版者
會議名稱2013 10th IEEE INTERNATIONAL CONFERENCE ON NETWORKING, SENSING AND CONTROL (ICNSC)
會議地點Evry, France
摘要In this paper, we propose a highly efficient VLSI architecture for 2-D dual-mode (supporting 5/3 and 9/7 lifting-based) Symmetric Mask-based Discrete Wavelet Transform (SMDWT) to improve the critical issue of the 2-D Lifting-based Discrete Wavelet Transform (LDWT), and then obtains the benefit of low-latency reduced complexity, and low transpose memory. The SMDWT also has the advantages of reduced complexity, regular signal coding, short critical path, reduced latency time, and independent subband coding processing. The transpose memory requirement of the N×N is 9N. The architecture is based on the parallel and folding scheme processing to achieve higher hardware utilization ratio and reduce the silicon area. It is suitable for Very Large Scale Integration (VLSI) implementation and can be applied to real-time operating of computer vision applications.
關鍵字Discrete wavelet transforms;CMOS integrated circuits;CMOS technology;Very large scale integration;Irrigation;Biomedical imaging;Image recognition
語言英文(美國)
收錄於
會議性質國際
校內研討會地點
研討會時間20130410~20130412
通訊作者
國別美國
公開徵稿
出版型式
出處
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