FPGA-based hardware design for scale-invariant feature transform
學年 107
學期 1
出版（發表）日期 2018-08-03
作品名稱 FPGA-based hardware design for scale-invariant feature transform
作品名稱（其他語言）
著者 SHIH-AN LI; WEI-YEN WANG; CHEN-CHIEN JAMES HSU; CHENG-KAI LU
單位
出版者
著錄名稱、卷期、頁數 IEEE Access 6, p.43850-43864
摘要 This paper proposes a novel hardware design method of scale-invariant feature transform (SIFT) algorithm for implementation on field-programmable gate array (FPGA). To reduce the computing costs, Gaussian kernels are calculated offline for use in Gaussian filters. To eliminate low-contrast points, the inverse of a Hessian matrix is required for hardware implementation, which results in poor performance because dividers are needed. To solve this problem, this paper presents a new mathematical derivation model to implement the low-contrast detection, avoiding the use of any dividers. For the implementation of the normalization module, a large number of dividers are required by traditional methods, which adversely affects the computational efficiency. This paper presents a new architecture using only one divider to implement the normalization function in hardware. Thanks to the parallel processing architecture proposed to design the image pyramid, SIFT detection, and SIFT descriptor, the computational efficiency of the SIFT algorithm is significantly improved. As a result of the proposed design method, the requirement of logic elements in the FPGA hardware is greatly reduced and system frequency is significantly increased. Experimental results show that the proposed hardware architecture outperforms existing techniques in terms of resource usage and computational efficiency for real-time image processing.
關鍵字 Hardware;Computer architecture;Field programmable gate arrays;Feature extraction;Computational efficiency;Real-time systems;Transforms
語言 en_US
ISSN 2169-3536
期刊性質 國外
收錄於 SCI ESCI
產學合作
通訊作者
審稿制度 否
國別 USA
公開徵稿
出版型式 ,電子版
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機構典藏連結 ( http://tkuir.lib.tku.edu.tw:8080/dspace/handle/987654321/117023 )

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