An Erase Efficiency Boosting Strategy for 3D Charge Trap NAND Flash
學年 106
學期 2
出版（發表）日期 2018-03-22
作品名稱 An Erase Efficiency Boosting Strategy for 3D Charge Trap NAND Flash
作品名稱（其他語言）
著者 Shuo-Han Chen; Yuan-Hao Chang; Yu-Pei Liang; Hsin-Wen Wei; Wei-Kuan Shih
單位
出版者
著錄名稱、卷期、頁數 IEEE Transactions on Computers 67(9), p.1246 - 1258
摘要 Owing to the fast-growing demands of larger and faster NAND flash devices, new manufacturing techniques have accelerated the down-scaling process of NAND flash memory. Among these new techniques, 3D charge trap flash is considered to be one of the most promising candidates for the next-generation NAND flash devices. However, the long erase latency of 3D charge trap flash becomes a critical issue. This issue is exacerbated because the distinct transient voltage shift phenomenon is worsened when the number of program/erase cycle increases. In contrast to existing works that aim to tackle the erase latency issue by reducing the number of block erases, we tackle this issue by utilizing the “multi-block erase” feature. In this work, an erase efficiency boosting strategy is proposed to boost the garbage collection efficiency of 3D charge trap flash via enabling multi-block erase inside flash chips. A series of experiments was conducted to demonstrate the capability of the proposed strategy on improving the erase efficiency and access performance of 3D charge trap flash. The results show that the erase latency of 3D charge trap flash memory is improved by 75.76 percent on average even when the P/E cycle reaches
關鍵字 Multi-block erase;3D charge trap;garbage collection;3D NAND flash;flash storage
語言 en_US
ISSN 0018-9340
期刊性質 國外
收錄於 SCI EI
產學合作
通訊作者
審稿制度 是
國別 USA
公開徵稿
出版型式 ,電子版,紙本
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