教師資料查詢 | 類別: 期刊論文 | 教師: 陳俊男 Chen,Chun-nan (瀏覽個人網頁)

標題:An FET With a Source Tunneling Barrier Showing Suppressed Short-Channel Effects for Low-Power Applications
學年106
學期1
出版(發表)日期2018/01/23
作品名稱An FET With a Source Tunneling Barrier Showing Suppressed Short-Channel Effects for Low-Power Applications
作品名稱(其他語言)
著者Hsieh, Yu-Feng; Chen, Si-Hua; Chen, Nan-Yow; Lee, Wen-Jay; Tsai, Jyun-Hwei; Chen, Chun-Nan; Chiang, Meng-Hsueh; Lu, Darsen D.; Kao, Kuo-Hsing
單位
出版者
著錄名稱、卷期、頁數IEEE TRANSACTIONS ON ELECTRON DEVICES ,65(3) ,P.855-859
摘要A device design technique using tunneling barriers (TBs) for reducing the short-channel effects (SCEs) is proposed. By introducing TBs at the source and drain junctions of a Si FET, the threshold voltage (Vth) rolloff can be significantly suppressed. This is because the TBs weaken the electrical coupling between drain bias and transmission/current spectrum in energy. Specifically, as compared with a conventional FET, the Vth roll-off for channel length reduction from 20 to 5 nm is mitigated by more than 40% when a thin TB is embedded at the source junction. This paper further reveals that the TB at the source junction dominates the physical mechanism minimizing the SCEs of the TBFET, and thus the device performance can be improved appreciably by removing the TB at the drain side and by decreasing the TB height at the source side.
關鍵字Field effect transistors;Silicon;Tunneling;Heterojunctions;Logic gates;Effective mass
語言英文
ISSN
期刊性質國外
收錄於SCI;
產學合作
通訊作者
審稿制度
國別美國
公開徵稿
出版型式,電子版,紙本
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