An 80x Analog-Implemented Time-Difference Amplifier for Delay-Line-Based Coarse-Fine Time-to-Digital Converters in 0.18-μm CMOS
學年 104
學期 1
出版(發表)日期 2015-08-13
作品名稱 An 80x Analog-Implemented Time-Difference Amplifier for Delay-Line-Based Coarse-Fine Time-to-Digital Converters in 0.18-μm CMOS
作品名稱(其他語言)
著者 Horng-Yuan Shih; Sheng-Kai Lin; Po-Shun Liao
單位
出版者
著錄名稱、卷期、頁數 IEEE Transactions on Very Large Scale Integration Systems 23(8), pp. 1528-1533
摘要 An analog-implemented time-difference amplifier applied for coarse-fine time-to-digital converters is presented in this paper. Implemented in 0.18-μm CMOS process, a time difference within 225 ps can be amplified 80× linearly under maximum frequency of 25 MHz. Measured maximum gain error is 4.1%. Measured output rms jitter is 84.5 ps under gain of 80×. The time amplifier consumes 1.7 mW under supply voltage of 1.8 V.
關鍵字 Coarse-fine time-to-digital converter (TDC);TDC;time-difference amplifier (TA)
語言 en_US
ISSN 1557-9999
期刊性質 國外
收錄於 SCI EI
產學合作
通訊作者 Horng-Yuan Shih
審稿制度
國別 USA
公開徵稿
出版型式 ,電子版
相關連結

機構典藏連結 ( http://tkuir.lib.tku.edu.tw:8080/dspace/handle/987654321/114939 )