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標題:All-digital duty-cycle corrector with synchronous and high accuracy output for double date rate synchronous dynamic random-access memory application
學年105
學期1
出版(發表)日期2017/01/30
作品名稱All-digital duty-cycle corrector with synchronous and high accuracy output for double date rate synchronous dynamic random-access memory application
作品名稱(其他語言)
著者Chih-Wei Tsai; Yu-Lung Lo; Chia-Chen Chang; Han-Ying Liu; Wei-Bin Yang; Kuo-Hsing Cheng
單位
出版者
著錄名稱、卷期、頁數Japanese Journal of Applied Physics, Vol. 56, No. 4S, pp. 04CF02-1-6
摘要A synchronous and highly accurate all-digital duty-cycle corrector (ADDCC), which uses simplified dual-loop architecture, is presented in this paper. To explain the operational principle, a detailed circuit description and formula derivation are provided. To verify the proposed design, a chip was fabricated through the 0.18-µm standard complementary metal oxide semiconductor process with a core area of 0.091 mm2. The measurement results indicate that the proposed ADDCC can operate between 300 and 600 MHz with an input duty-cycle range of 40–60%, and that the output duty-cycle error is less than 1% with a root-mean-square jitter of 3.86 ps.
關鍵字
語言英文(美國)
ISSN
期刊性質國外
收錄於SCI;EI;
產學合作
通訊作者
審稿制度
國別日本
公開徵稿
出版型式,電子版
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