教師資料查詢 | 類別: 期刊論文 | 教師: 楊維斌 Web-bin Yang (瀏覽個人網頁)

標題:A Fast-Lock and Low-Power DLL-Based Clock Generator Applied for DDR4
學年105
學期1
出版(發表)日期2016/11/22
作品名稱A Fast-Lock and Low-Power DLL-Based Clock Generator Applied for DDR4
作品名稱(其他語言)
著者Yu-Lung Lo; Wei-Bin Yang; Han-Hsien Wang; Cing-Huan Chen; Zi-Ang Huang
單位
出版者
著錄名稱、卷期、頁數Microsystem Technologies
摘要This paper presents a fast-lock and low-power delay-locked loop (DLL) circuit applied for DDR4. The proposed modified phase detector and modified charge pump can reduce locking time as well as static phase error. The glitch elimination circuit reduces glitches in the PD for reducing the glitch power. The phase interpolator and phase combiner circuit are used to generate four output frequencies: 0.2, 0.4, 0.8, and 1.6 GHz. The design is fabricated through a 0.18-μm standard CMOS process with a supply voltage of 1.8 V. The simulation results indicate that the lock time is less than 20 cycles and the power consumption of the DLL is 15.14 mW at 1.6 GHz. The active die area of the proposed DLL-based clock generator is 0.51 mm2.
關鍵字
語言英文(美國)
ISSN
期刊性質國外
收錄於SCI;EI;
產學合作
通訊作者Wei-Bin Yang
審稿制度
國別德國
公開徵稿
出版型式,電子版
相關連結
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