Wide‑range CMOS reference clock generator with a dynamic duty cycle scaling mechanism at a 0.9‑V supply voltage
學年 106
學期 1
出版（發表）日期 2018-01-01
作品名稱 Wide‑range CMOS reference clock generator with a dynamic duty cycle scaling mechanism at a 0.9‑V supply voltage
作品名稱（其他語言）
著者 Wei-Bin Yang; Yu-Lung Lo; Kuo-Ning Chang; Yu-Yao Lin
單位
出版者
著錄名稱、卷期、頁數 Microsystem Technologies 24(1), p.71–78
摘要 This paper presents a wide-range CMOS reference clock generator with a dynamic duty cycle scaling mechanism. A new duty-cycle-to-voltage converter (DCVC) is proposed for the clock generator, which requires only the duty cycles of differential 25-MHz input signals. When these duty cycles are set into the DCVC, dual control voltages, namely VP and VN with positive and negative control duty cycle coefficients, respectively, are produced to manage the current sources of the differential voltage-controlled ring oscillator and supply a wide range of frequency channels. The proposed clock generator can supply a stable output clock with a wide range of frequencies from 37 kHz to 34 MHz. Notably, the wide-range CMOS reference clock generator can also be used in a universal serial bus hub or in wide band applications with low supply voltages and small areas.
關鍵字
語言 en_US
ISSN
期刊性質 國外
收錄於 SCI EI
產學合作
通訊作者
審稿制度 是
國別 DEU
公開徵稿
出版型式 ,電子版
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