教師資料查詢 | 類別: 期刊論文 | 教師: 蔡奇謚 Chi-yi Tsai (瀏覽個人網頁)

標題:Low-cost and high-speed hardware implementation of contrast-preserving image dynamic range compression for full-HD video enhancement
學年104
學期1
出版(發表)日期2015/08/01
作品名稱Low-cost and high-speed hardware implementation of contrast-preserving image dynamic range compression for full-HD video enhancement
作品名稱(其他語言)
著者Li, Shih-An; Tsai, Chi-Yi
單位
出版者
著錄名稱、卷期、頁數Image Processing 9(8), pp.605-614
摘要This study presents a cost-efficient and high-performance field programmable gate array (FPGA)-based hardware implementation of a contrast-preserving image dynamic range compression algorithm, which is an important function used in modern digital video cameras and displays to improve visual quality of standard dynamic range colour images (8 bits/channel). To achieve this purpose, a hardware-friendly approximation to an existing fast dynamic range compression with local contrast preservation (FDRCLCP) algorithm is proposed. The computation of the proposed approximated FDRCLCP algorithm requires only fixed-point unsigned binary addition, multiplication, and bit-shifting. Moreover, the proposed hardware implementation uses a line buffer instead of a frame buffer to process whole image data. These advantages significantly improve throughput performance and reduce memory requirement of the system. The FPGA implementation of the proposed algorithm requires only about 98 K bits on-chip memory and achieves about 170.24 MHz operating frequency by using an Altera Cyclone II device. This is a large improvement compared with the existing results as it is quick enough to process full high-definition videos (1920 × 1080 pixels) at least 80 frames per second using a low-cost FPGA device.
關鍵字approximation theory; data compression; field programmable gate arrays; image colour analysis; image enhancement; video coding
語言英文
ISSN1751-9659
期刊性質國外
收錄於SCI;EI;
產學合作
通訊作者
審稿制度
國別英國
公開徵稿
出版型式,電子版,紙本
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