Reconfigurable multiple scan-chains for reducing test application time of SOCs
學年 93
學期 2
發表日期 2005-05-23
作品名稱 Reconfigurable multiple scan-chains for reducing test application time of SOCs
作品名稱（其他語言）
著者 Rau, Jiann-chyi; Chien, Chih-lung; Ma, Jia-shing
作品所屬單位 淡江大學電機工程學系
出版者 N.Y.: Institute of Electrical and Electronic Engineers (IEEE)
會議名稱 Circuits and Systems, 2005. ISCAS 2005. IEEE International Symposium on
會議地點 Kobe, Japan
摘要 We propose an algorithm, based on a framework of reconfigurable multiple scan-chains for a system-on-chip, to minimize test application time. For the framework, the control signal combination causes the computing time to increase exponentially. The algorithm we propose introduces a heuristic control signal selection method to solve this problem. We also minimize the test application time by using the balancing method to assign registers into multiple scan-chains. It could show significant reductions in test application times and computing times.
關鍵字
語言 en
收錄於
會議性質 國際
校內研討會地點
研討會時間 20050523~20050526
通訊作者
國別 JPN
公開徵稿
出版型式
出處 Circuits and Systems, 2005. ISCAS 2005. IEEE International Symposium on (Volume:6 ), pp.5846-5849
相關連結

機構典藏連結 ( http://tkuir.lib.tku.edu.tw:8080/dspace/handle/987654321/39042 )

機構典藏連結
SDGS 產業創新與基礎設施