教師資料查詢 | 類別: 會議論文 | 教師: 饒建奇 Jiann-chyi Rau (瀏覽個人網頁)

標題:Reconfigurable multiple scan-chains for reducing test application time of SOCs
學年93
學期2
發表日期2005/05/23
作品名稱Reconfigurable multiple scan-chains for reducing test application time of SOCs
作品名稱(其他語言)
著者Rau, Jiann-chyi; Chien, Chih-lung; Ma, Jia-shing
作品所屬單位淡江大學電機工程學系
出版者N.Y.: Institute of Electrical and Electronic Engineers (IEEE)
會議名稱Circuits and Systems, 2005. ISCAS 2005. IEEE International Symposium on
會議地點Kobe, Japan
摘要We propose an algorithm, based on a framework of reconfigurable multiple scan-chains for a system-on-chip, to minimize test application time. For the framework, the control signal combination causes the computing time to increase exponentially. The algorithm we propose introduces a heuristic control signal selection method to solve this problem. We also minimize the test application time by using the balancing method to assign registers into multiple scan-chains. It could show significant reductions in test application times and computing times.
關鍵字
語言英文
收錄於
會議性質國際
校內研討會地點
研討會時間20050523~20050526
通訊作者
國別日本
公開徵稿
出版型式
出處Circuits and Systems, 2005. ISCAS 2005. IEEE International Symposium on (Volume:6 ), pp.5846-5849
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