A 1.2 V 500 MHz 32-bit carry-lookahead adder
學年 90
學期 1
發表日期 2001-09-02
作品名稱 A 1.2 V 500 MHz 32-bit carry-lookahead adder
作品名稱（其他語言）
著者 鄭國興; Cheng, Kuo-hsing; Lee, Wen-shiuan; Huang, Yung-chong
作品所屬單位 淡江大學電機工程學系
出版者 Institute of Electrical and Electronics Engineers (IEEE)
會議名稱 Electronics, Circuits and Systems, 2001. ICECS 2001. The 8th IEEE International Conference on
會議地點 Malta
摘要 In this paper a 1.2 V 32-bit carry lookahead adder is proposed for high speed, low voltage applications. The proposed new 32-bit adder uses Non-full Voltage Swing True-Single-Phase-Clocking Logic (NSTSPC) to implement the proposed carry lookahead adder. Because the internal node of NSTSPC was non-full swing, its operation speed would be higher than the conventional TSPC. Moreover, the supply voltage for the new adder is 1.2 V, thus the power dissipation would also be reduced. The 32-bit CLA adder using 0.35 μm 1P4M CMOS technology with 1.2 V power supply could be operated at a 500 MHz clock frequency.
關鍵字
語言 en
收錄於
會議性質 國際
校內研討會地點
研討會時間 20010902~20010905
通訊作者
國別 MLT
公開徵稿
出版型式 紙本
出處 Electronics, Circuits and Systems, 2001. ICECS 2001. The 8th IEEE International Conference on (Volume:2 ), pp.765-768
相關連結

機構典藏連結 ( http://tkuir.lib.tku.edu.tw:8080/dspace/handle/987654321/38845 )

機構典藏連結