A novel all digital phase locked loop (ADPLL) with ultra fast locked time and high oscillation frequency
學年 90
學期 1
發表日期 2001-09-12
作品名稱 A novel all digital phase locked loop (ADPLL) with ultra fast locked time and high oscillation frequency
作品名稱（其他語言）
著者 鄭國興; Cheng, Kuo-hsing; Chen, Yu-jung
作品所屬單位 淡江大學電機工程學系
出版者 Institute of Electrical and Electronics Engineers (IEEE)
會議名稱 ASIC/SOC Conference, 2001. Proceedings. 14th Annual IEEE International
會議地點 Arlington, VA, USA
摘要 In this paper a new architecture for all digital phase locked loop (ADPLL) is proposed The new architecture is based on the ADPLL architecture proposed by Motorola in 1995 but modified in some block A new binary search decision scheme was used to accelerate the frequency acquisition process. It can reduce the chip area and increase the operating frequency. In this design, a 14-bit control word is used to control the digital control oscillator. The new type ADPLL has been designed and implemented by TSMC's 0-35 μ IP4M CMOS process for 3.3V applications. The phase lock process takes 20-reference cycle, and the maximum frequency of the proposed ADPLL is about 820MHz.
關鍵字
語言 en
收錄於
會議性質 國際
校內研討會地點
研討會時間 20010912~20010915
通訊作者
國別 USA
公開徵稿
出版型式
出處 ASIC/SOC Conference, 2001. Proceedings. 14th Annual IEEE International, pp.139-143
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