A low-power high driving ability voltage control oscillator used in PLL
學年 89
學期 2
發表日期 2001-05-06
作品名稱 A low-power high driving ability voltage control oscillator used in PLL
作品名稱(其他語言)
著者 鄭國興; Cheng, Kuo-hsing; Yang, Wei-bin; Chung, Chun-fu
作品所屬單位 淡江大學電機工程學系
出版者 Institute of Electrical and Electronics Engineers (IEEE)
會議名稱 Circuits and Systems, 2001. ISCAS 2001. The 2001 IEEE International Symposium on
會議地點 Sydney, NSW, Australia
摘要 Modern high speed CMOS processors using on-chip phase-locked-loops often require a clock buffer with stringent specifications on the signal's rise time and fall time rather than on the buffer's delay time. For these applications we propose a novel voltage controlled oscillator (VCO) with split path CMOS driver. It can be proposed to reduce the total power consumption and phase errors of the PLL. The proposed VCO with the split-path CMOS driver has low power consumption and lower area requirement than that achievable by the traditional tapered CMOS buffer.
關鍵字
語言 en
收錄於
會議性質 國際
校內研討會地點
研討會時間 20010506~20010509
通訊作者
國別 AUS
公開徵稿
出版型式 紙本
出處 Circuits and Systems, 2001. ISCAS 2001. The 2001 IEEE International Symposium on (Volume:4 ), pp.614-617
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