| A new logic synthesis and optimization procedure | |
|---|---|
| 學年 | 89 |
| 學期 | 2 |
| 發表日期 | 2001-05-06 |
| 作品名稱 | A new logic synthesis and optimization procedure |
| 作品名稱（其他語言） | |
| 著者 | 鄭國興; Cheng, Kuo-hsing; Hsieh, Ven-chieh |
| 作品所屬單位 | 淡江大學電機工程學系 |
| 出版者 | Institute of Electrical and Electronics Engineers (IEEE) |
| 會議名稱 | Circuits and Systems, 2001. ISCAS 2001. The 2001 IEEE International Symposium on |
| 會議地點 | Sydney, NSW, Australia |
| 摘要 | The objective of this work is to develop a new logic circuit synthesis and optimization procedure for arbitrary logic function. Following the procedure, we may get a new high performance logic circuit family, which has low power consumption, low power-delay product, area efficiency and suitable for low supply voltage. The new logic family based upon the proposed design procedures has certain advantage over CMOS, DVL and DPL in most cases. |
| 關鍵字 | |
| 語言 | en |
| 收錄於 | |
| 會議性質 | 國際 |
| 校內研討會地點 | |
| 研討會時間 | 20010506~20010509 |
| 通訊作者 | |
| 國別 | AUS |
| 公開徵稿 | |
| 出版型式 | 紙本 |
| 出處 | Circuits and Systems, 2001. ISCAS 2001. The 2001 IEEE International Symposium on (Volume:4 ), pp.182-185 |
| 相關連結 |
機構典藏連結 ( http://tkuir.lib.tku.edu.tw:8080/dspace/handle/987654321/38840 ) |
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