教師資料查詢 | 類別: 會議論文 | 教師: 鄭國興 CHENG KUO-HSING (瀏覽個人網頁)

標題:A new logic synthesis and optimization procedure
學年89
學期2
發表日期2001/05/06
作品名稱A new logic synthesis and optimization procedure
作品名稱(其他語言)
著者鄭國興; Cheng, Kuo-hsing; Hsieh, Ven-chieh
作品所屬單位淡江大學電機工程學系
出版者Institute of Electrical and Electronics Engineers (IEEE)
會議名稱Circuits and Systems, 2001. ISCAS 2001. The 2001 IEEE International Symposium on
會議地點Sydney, NSW, Australia
摘要The objective of this work is to develop a new logic circuit synthesis and optimization procedure for arbitrary logic function. Following the procedure, we may get a new high performance logic circuit family, which has low power consumption, low power-delay product, area efficiency and suitable for low supply voltage. The new logic family based upon the proposed design procedures has certain advantage over CMOS, DVL and DPL in most cases.
關鍵字
語言英文
收錄於
會議性質國際
校內研討會地點
研討會時間20010506~20010509
通訊作者
國別澳洲
公開徵稿
出版型式紙本
出處Circuits and Systems, 2001. ISCAS 2001. The 2001 IEEE International Symposium on (Volume:4 ), pp.182-185
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