The non-full voltage swing TSPC (NSTSPC) logic design
學年 88
學期 1
發表日期 2000-08-28
作品名稱 The non-full voltage swing TSPC (NSTSPC) logic design
作品名稱（其他語言）
著者 Cheng, Kuo-hsing; Huang, Yung-chong
作品所屬單位 淡江大學電機工程學系
出版者 N.Y.: Institute of Electrical and Electronic Engineers (IEEE)
會議名稱 ASICs, 2000. AP-ASIC 2000. Proceedings of the Second IEEE Asia Pacific Conference on
會議地點 Cheju, Korea
摘要 In this paper, a new TSPC logic circuit is proposed for low-voltage high-speed applications. The proposed new circuit using non-full voltage swing scheme in internal nodes to reduce logic evaluation time and to save dynamic power. Thus the advantages of the new TSPC logic circuit over the conventional TSPC logic circuit are speed and power-delay product. Based upon the 0.35 μm CMOS technology, the proposed new TSPC logic has 25% improvement over the conventional TSPC circuit in power-delay product. The new circuit can be operated at 250 MHz with 1.2 V supply voltage In this paper, a new TSPC logic circuit is proposed for low-voltage high-speed applications. The proposed new circuit using non-full voltage swing scheme in internal nodes to reduce logic evaluation time and to save dynamic power. Thus the advantages of the new TSPC logic circuit over the conventional TSPC logic circuit are speed and power-delay product. Based upon the 0.35 μm CMOS technology, the proposed new TSPC logic has 25% improvement over the conventional TSPC circuit in power-delay product. The new circuit can be operated at 250 MHz with 1.2 V supply voltage.
關鍵字
語言 en
收錄於
會議性質 國際
校內研討會地點
研討會時間 20000828~20000830
通訊作者
國別 KOR
公開徵稿
出版型式 紙本
出處 ASICs, 2000. AP-ASIC 2000. Proceedings of the Second IEEE Asia Pacific Conference on, pp.37-40
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