標題:The Design and implementation of DCT/IDCT Chip with Novel Architecture |
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學年 | 88 |
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學期 | 2 |
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發表日期 | 2000/05/01 |
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作品名稱 | The Design and implementation of DCT/IDCT Chip with Novel Architecture |
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作品名稱(其他語言) | |
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著者 | 鄭國興; Cheng, Kuo-hsing; Huang, Chih-sheng; Lin, Chun-pin |
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作品所屬單位 | 淡江大學電機工程學系 |
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出版者 | N.Y.: Institute of Electrical and Electronic Engineers (IEEE) |
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會議名稱 | Circuits and Systems, 2000. Proceedings. ISCAS 2000 Geneva. The 2000 IEEE International Symposium on |
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會議地點 | Geneva, Switzerland |
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摘要 | In the paper, an efficient VLSI architecture for a 8×8 two-dimensional discrete cosine transform and inverse discrete cosine transform (2-D DCT/IDCT) with a new 1-D DCT/IDCT algorithm is presented. The proposed new algorithm makes sure all coefficients are positive to simplify the design of multipliers and the coefficients have less round-off error than Lee's algorithm. For computing 2-D DCT/IDCT, the row-column decomposition method is used, and the design of 1-D DCT/IDCT requires only 9 multipliers and 21 adders/subtractors. This chip is synthesized with 0.6 μm standard cell library and 1P3M CMOS technology, and it can be operated up to 100 MHz;In the paper, an efficient VLSI architecture for a 8×8 two-dimensional discrete cosine transform and inverse discrete cosine transform (2-D DCT/IDCT) with a new 1-D DCT/IDCT algorithm is presented. The proposed new algorithm makes sure all coefficients are positive to simplify the design of multipliers and the coefficients have less round-off error than Lee's algorithm. For computing 2-D DCT/IDCT, the row-column decomposition method is used, and the design of 1-D DCT/IDCT requires only 9 multipliers and 21 adders/subtractors. This chip is synthesized with 0.6 μm standard cell library and 1P3M CMOS technology, and it can be operated up to 100 MHz |
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關鍵字 | |
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語言 | 英文 |
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會議性質 | 國際 |
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校內研討會地點 | |
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研討會時間 | |
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通訊作者 | |
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國別 | 瑞士 |
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公開徵稿 | |
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出版型式 | 紙本 |
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出處 | Circuits and Systems, 2000. Proceedings. ISCAS 2000 Geneva. The 2000 IEEE International Symposium on (Volume:4 ), pp.741-744 |
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