教師資料查詢 | 類別: 會議論文 | 教師: 鄭國興 CHENG KUO-HSING (瀏覽個人網頁)

標題：The Design and implementation of DCT/IDCT Chip with Novel Architecture
學年88
學期2
發表日期2000/05/01
作品名稱The Design and implementation of DCT/IDCT Chip with Novel Architecture
作品名稱（其他語言）
著者鄭國興; Cheng, Kuo-hsing; Huang, Chih-sheng; Lin, Chun-pin
作品所屬單位淡江大學電機工程學系
出版者N.Y.: Institute of Electrical and Electronic Engineers (IEEE)
會議名稱Circuits and Systems, 2000. Proceedings. ISCAS 2000 Geneva. The 2000 IEEE International Symposium on
會議地點Geneva, Switzerland
摘要In the paper, an efficient VLSI architecture for a 8×8 two-dimensional discrete cosine transform and inverse discrete cosine transform (2-D DCT/IDCT) with a new 1-D DCT/IDCT algorithm is presented. The proposed new algorithm makes sure all coefficients are positive to simplify the design of multipliers and the coefficients have less round-off error than Lee's algorithm. For computing 2-D DCT/IDCT, the row-column decomposition method is used, and the design of 1-D DCT/IDCT requires only 9 multipliers and 21 adders/subtractors. This chip is synthesized with 0.6 μm standard cell library and 1P3M CMOS technology, and it can be operated up to 100 MHz;In the paper, an efficient VLSI architecture for a 8×8 two-dimensional discrete cosine transform and inverse discrete cosine transform (2-D DCT/IDCT) with a new 1-D DCT/IDCT algorithm is presented. The proposed new algorithm makes sure all coefficients are positive to simplify the design of multipliers and the coefficients have less round-off error than Lee's algorithm. For computing 2-D DCT/IDCT, the row-column decomposition method is used, and the design of 1-D DCT/IDCT requires only 9 multipliers and 21 adders/subtractors. This chip is synthesized with 0.6 μm standard cell library and 1P3M CMOS technology, and it can be operated up to 100 MHz
關鍵字
語言英文
收錄於
會議性質國際
校內研討會地點
研討會時間
通訊作者
國別瑞士
公開徵稿
出版型式紙本
出處Circuits and Systems, 2000. Proceedings. ISCAS 2000 Geneva. The 2000 IEEE International Symposium on (Volume:4 ), pp.741-744
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