教師資料查詢 | 類別: 會議論文 | 教師: 江正雄 CHIANG JEN-SHIUN (瀏覽個人網頁)

標題:A 3.3 V two-stage fourth-order sigma-delta modulator with gain compensation technique
學年87
學期1
發表日期1998/11/24
作品名稱A 3.3 V two-stage fourth-order sigma-delta modulator with gain compensation technique
作品名稱(其他語言)
著者江正雄; Chiang, Jen-shiun; Chou, Pao-chu
作品所屬單位淡江大學電機工程學系
出版者Institute of Electrical and Electronics Engineers (IEEE)
會議名稱Circuits and Systems, 1998. IEEE APCCAS 1998. The 1998 IEEE Asia-Pacific Conference on
會議地點Chiangmai, Thailand
摘要We propose a multistage fourth order sigma-delta (ΣΔ) modulator with reduced sensitivity to the gain of operating amplifier. In the low voltage high order ΣΔ modulator, the gain of the operating amplifier is usually the most critical problem of the design. In order to overcome the difficulties of the high gain low voltage operating amplifier, we try to use medium gain operating amplifiers to design a fourth order multistage ΣΔ modulator, and find that it functions very well. The modulator is realized in a 0.5 μm DPDM process with an active area of 1.8 mm2. The HSPICE simulation shows this ΣΔ modulator with a maximum signal-to-noise-ratio (SNR) of 91 dB.
關鍵字
語言英文
收錄於
會議性質國際
校內研討會地點
研討會時間19981124~19981127
通訊作者
國別泰國
公開徵稿
出版型式紙本
出處Circuits and Systems, 1998. IEEE APCCAS 1998. The 1998 IEEE Asia-Pacific Conference on, pp.1-4
相關連結
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