教師資料查詢 | 類別: 會議論文 | 教師: 江正雄 CHIANG JEN-SHIUN (瀏覽個人網頁)

標題:A 3.3 V all digital phase-locked loop with small DCO hardware and fast phase lock
學年86
學期2
發表日期1998/05/31
作品名稱A 3.3 V all digital phase-locked loop with small DCO hardware and fast phase lock
作品名稱(其他語言)
著者江正雄; Chiang, Jen-shiun; Chen, Kuang-yuan
作品所屬單位淡江大學電機工程學系
出版者Institute of Electrical and Electronics Engineers (IEEE)
會議名稱Circuits and Systems, 1998. ISCAS '98. Proceedings of the 1998 IEEE International Symposium on
會議地點
摘要In this paper, we aim to design and implement an all digital phase-locked loop (ADPLL) circuit. The core of the ADPLL is the switch-tuning digital control oscillator (DCO). Our design of the DCO has features of small hardware cost. This ADPLL has characteristics of fast frequency locking, full digitization, easy design and implementation, and good stability. It is suitable to be used as the clock generator for high performance microprocessors. A prototype of this ADPLL chip is designed and implemented by TSMC's 0.6 μm SPDM CMOS process. The simulation shows that this chip can operate in the range between 60 MHz and 400 MHz, and operates at 4× the reference clock frequency. The phase lock process is 47 clock cycles, and the phase error is less than 0.1 ns. The IC consists of 4026 MOS transistors and the core size of the chip layout is 923 μm×921 μm.
關鍵字
語言英文
收錄於
會議性質國際
校內研討會地點
研討會時間19980531~19980603
通訊作者
國別Monterey, CA, USA;USA
公開徵稿
出版型式紙本
出處Circuits and Systems, 1998. ISCAS '98. Proceedings of the 1998 IEEE International Symposium on (Volume:3 ), pp.554-557
相關連結
Google+ 推薦功能,讓全世界都能看到您的推薦!