The design of a delta-sigma modulator with low clock feedthrough noise, op-amp gain compensation, and more correctly transferring charges between capacitors | |
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學年 | 85 |
學期 | 2 |
發表日期 | 1997-06-09 |
作品名稱 | The design of a delta-sigma modulator with low clock feedthrough noise, op-amp gain compensation, and more correctly transferring charges between capacitors |
作品名稱(其他語言) | |
著者 | Chiang, Jen-shiun; Hu, Chih-wei |
作品所屬單位 | 淡江大學電機工程學系 |
出版者 | N.Y.: Institute of Electrical and Electronic Engineers (IEEE) |
會議名稱 | Circuits and Systems, 1997. ISCAS '97., Proceedings of 1997 IEEE International Symposium on |
會議地點 | Hong Kong |
摘要 | The performance of a delta-sigma modulator (Δ ΣM) is degraded due to the low op-amp gain, the clock feedthrough noise, and the right or fault of charge transferring between capacitors. Hurst et al. in 1993 suggested an architecture which uses reduced sensitivity to the op-amp gain. Since the low op-amp gain is much easier to design and makes the design of a Δ ΣM become very easy. However, they do not overcome the noise effect of the Δ ΣM. Here, another design is proposed and the effect of noise is reduced |
關鍵字 | |
語言 | en |
收錄於 | |
會議性質 | 國際 |
校內研討會地點 | |
研討會時間 | 19970609~19970612 |
通訊作者 | |
國別 | HKG |
公開徵稿 | |
出版型式 | |
出處 | Circuits and Systems, 1997. ISCAS '97., Proceedings of 1997 IEEE International Symposium on, vol.3, pp.2016-2019 |
相關連結 |
機構典藏連結 ( http://tkuir.lib.tku.edu.tw:8080/dspace/handle/987654321/38561 ) |
SDGS | 永續城市與社區,負責任的消費與生產,夥伴關係,優質教育,尊嚴就業與經濟發展,產業創新與基礎設施 |